This invention generally relates to electronic systems, and more particularly relates to common mode feedback bias for low voltage opamps.
FIG. 1 shows a prior art two stage fully differential opamp for low voltage systems. Differential pair transistors M1 and M2 with active loads transistors M3 and M4 form the first stage, and common source amplifier transistors M5 and M6 with active load transistors M11 and M12 serve as a class-A output stage driving the output terminals OUTP and OUTM. Miller pole-splitting compensation is shown. Common mode feedback is applied with differential pair transistors M7 and M8, loaded with current mirror transistor M9 working into the first stage active load devices M3 and M4. The desired level of output common mode voltage is applied at terminal CMDES, and the actual output common mode level is sensed with a pair of matched averaging resistors R1 and R2. The common mode feedback drives the observed level to the desired level with the loop gain. Small capacitors C1 and C2 bypassing R1 and R2 improve the common mode loop phase margin.
This topology works fairly well, but it is possible that if the opamp is used in a circuit with overall resistive feedback, the common mode loop can settle in a stable operating point which drives both the output terminals to the positive rail. Suppose that in either an initial startup condition or a transient condition both the input terminals INP and INM are close to the positive rail. This will leave the input stage tail current source transistor M13 with virtually no drain voltage, reducing its output current to very small levels. This will cause transistors M3 and M4 to lose control of the common mode output level at the output of the first stage, and second stage devices M5 and M6 will be below threshold. This lifts the output voltage close to the positive rail. If the feedback around the opamp is resistive, with no other bias source ensuring proper input terminal common mode biasing, then the input terminals will have their high levels latched, and the opamp will be in a stable but virtually useless state.
In general, this troublesome behavior is caused by the conflict between two common mode feedback loops, one being the intended one through the differential pair of transistors M7 and M8 to accurately control the output level, and the other the path through the overall feedback resistors through the input pair of transistors M1 and M2. Usually the high drain resistance of tail source transistor M13 degenerates the second feedback path, leaving only the intended one to act in the circuit. But if the input voltage is high enough to send transistor M13 into the ohmic region, its drain resistance falls markedly, increasing the common mode gain through the opamp signal path. Since for a two stage amplifier the common mode gain is positive, this path may take over and latch the opamp state.
Prior art designs have addressed this problem by including two additional devices M15 and M16 as shown in FIG. 2. An appropriate bias voltage is applied to terminal BIAS such that in normal operation, with the input terminals at their desired common mode level, transistors M15 and M16 will be held subthreshold by the tail voltage at the sources of transistors M1 and M2. The common mode feedback loop operated normally, and transistors M15 and M16 do not contribute any noise into the opamp. However, if the input levels ever rise toward the positive rail, transistors M15 and M16 will conduct, maintaining bias current to transistors M3 and M4, and ensuring that the common mode loop will not lose control and latch.
This simple arrangement unfortunately becomes unusable at very low supply voltages. Generally, the lower supply limit for an opamp of this topology will be determined by the supply voltage where tail current transistor M13 goes into the ohmic region at the prescribed input common mode level. Therefore, operating the opamp at the minimum supply voltage means that there is no value of the BIAS voltage in FIG. 2 which will leave transistors M15 and M16 off, and not degrading performance, yet enabling transistors M15 and M16 to catch the condition that transistor M13 is entering the ohmic region.
An opamp with common mode feedback bias includes: a first differential pair having first and second inputs; active load devices coupled to the first differential pair; a common mode feedback circuit coupled to the active load devices for controlling the active load devices; a second differential pair having a first input coupled to the first input of the first differential pair and a second input coupled to the second input of the first differential pair; and current drivers having control nodes coupled to the second differential pair and outputs coupled to the active load devices.